The present invention relates to an arithmetic unit included in a digital signal processor to execute division operations.
Recently, with the trend toward introduction of digital systems into the field of mobile communications, the digital signal processor (hereinafter simply referred to as DSP) has been highlighted as a processor to be built in such an apparatus as a portable telephone.
In the digital mobile communications as described above, low power consumption aiming at prolongation of the operation time of a battery used and an improvement in the throughput for execution of a complicated application program in, for example, a voice codec are required of the DSP. Reduction in costs is also required of the DSP.
In the DSP, division is sometimes executed by using a nonrestoring division algorithm (see, for example, "DSP 56116 Digital Signal Processor User's Manual" by Motorola Inc., 1990). An example of a prior art arithmetic unit for dividing data of predetermined n bits by data of n bits pursuant to the nonrestoring division algorithm will be described hereunder with reference to a schematic block diagram shown in FIG. 5.
In FIG. 5, a register 101 having a length of n bits holds a divisor. A register 102 having a length of 2n bits holds "0" at its upper n bits and a dividend at its lower n bits. A shifter 103 shifts data from the register 102 by one bit to the left. In the shifter 103, the least significant bit is initially inserted with "0" and subsequently inserted with an inversion of a positive or negative sign signal indicative of a result of calculation. The upper n bits are delivered to an arithmetic and logic circuit 104 to be described later, and the lower n bits are delivered to the lower bits of the register 102. The arithmetic and logic circuit 104 having a bit length of n is connected to the register 101 and shifter 103, and it performs addition or subtraction in accordance with a signal indicative of positive or negative sign from the register 102 and delivers a result of calculation to the upper n bits of the register 102.
The arithmetic unit constructed as described above and its operation to execute division will be detailed below.
Firstly, the arithmetic and logic circuit 104 decides whether of data held by the register 102 is positive or negative. When the data is positive, it is meant thereby that a divisor could be subtracted. When the data is negative, an operation of shifting the data by one bit to the left and adding the divisor will result in the same calculation as subtraction executed at the data shifted to the left by one bit. Accordingly, the data held by the register 102 is shifted by one bit to the left by means of the shifter 103. After being shifted, in the initial step the least significant bit of the shifter 103 is fulfilled with "0" and in a subsequent step it is inserted with an inversion of a positive or negative signal indicative of a result of calculation. As a result of shifting, the upper n bits correspond to a remainder of an upper digit portion of a dividend and they are delivered to the arithmetic and logic circuit 104. As a result of shifting, the lower n bits correspond to a lower digit portion of the dividend and a number indicative of a quotient result up to the current step and they are delivered to the register 102. Next, if the initially decided value of the register 102 is negative, the value of the register 101 and an output of the shifter 103 are added together by means of the arithmetic and logic circuit 104. If the decided value of the register 102 is non-negative, the value of the register 101 is subtracted from the output of the shifter 103 by means of the arithmetic and logic circuit 104 and a result is stored in the register 102. Thereafter, the sign of the data in the register 102 is again decided. The above operation is repeated (n-1) times and finally, the positive or negative sign of the register 102 is decided. If negative, "0" is set to the least significant bit of the register 102 and if non-negative, "1" is set. As a result, a quotient is stored at the lower n bits of the register 102.
In the prior art example of an arithmetic unit, however, the shifter 103 is required to have a bit length of 2n and a path extending from the shifter 103 to the register 102 is needed, thus increasing the amount of hardware.
Further, which one of addition and subtraction the arithmetic and logic circuit 104 is to perform is controlled by a signal indicative of the positive or negative sign of data held by the register 102, thus making the control operation complicated. In order to realize the complicated control operation, large amount of hardware is needed. The large-sized hardware makes the DSP expensive and has many operating portions, raising a problem that consumptive power is increased.